//****************************************Copyright (c)***********************************//
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//Copyright(C) 正点原子 2018-2028
//All rights reserved                               
//----------------------------------------------------------------------------------------
// File name:           sdram_cmd
// Last modified Date:  2018/3/18 8:41:06
// Last Version:        V1.0
// Descriptions:        SDRAM 命令控制模块
//----------------------------------------------------------------------------------------
// Created by:          正点原子
// Created date:        2018/3/18 8:41:06
// Version:             V1.0
// Descriptions:        The original version
//
//----------------------------------------------------------------------------------------
//****************************************************************************************//

`timescale 1ns/1ns

module tb_sdram();

//reg define
reg         clock_50m;                    //50Mhz时钟
reg         rst_n;                        //复位
                                          
//wire define                             
wire        sdram_clk;                    //SDRAM 芯片时钟 
wire        sdram_cke;                    //SDRAM 时钟有效 
wire        sdram_cs_n;                   //SDRAM 片选
wire        sdram_ras_n;                  //SDRAM 行有效
wire        sdram_cas_n;                  //SDRAM 列有效
wire        sdram_we_n;                   //SDRAM 写有效
wire [ 1:0] sdram_ba;                     //SDRAM Bank地址   
wire [12:0] sdram_addr;                   //SDRAM 行/列地址  
wire [15:0] sdram_data;                   //SDRAM 数据
wire [ 1:0] sdram_dqm;                    //SDRAM 数据掩码 
                                          
wire [ 1:0] led;                          //led

//*****************************************************
//**                    main code
//***************************************************** 

//初始化时钟和复位
initial begin
  clock_50m = 0;
  rst_n     = 0;                      
  #100                                    //100ns
  rst_n     = 1;
end

//系统时钟50Mhz,周期20ns
always #20 clock_50m = ~clock_50m; 

//修改参数
defparam u_sdram_rw_test.u_led_disp.LED_CNT = 5;    //修改LED闪烁时间

defparam u_sdram_rw_test.ADDR_MAX = 24'd2048;       //修改最大地址

defparam u_sdram_rw_test.LEN = 10'd512;             //修改突发长度
defparam u_sdram_rw_test.u_sdram_top.u_sdram_controller.u_sdram_cmd.BURST_LENGTH = 3'b111;//修改模式寄存器中突发长度

defparam u_sdram_rw_test.u_sdram_test.WR_CNT = 24'd2048;
defparam u_sdram_rw_test.u_sdram_test.RD_CNT = 24'd2048;

//SDRAM
sdram_rw_test u_sdram_rw_test(
    .clk            (clock_50m),          //FPGA系统时钟50M
    .rst_n          (rst_n),              //按键复位，低电平有效
        
    .sdram_clk      (sdram_clk),          //SDRAM 芯片时钟
    .sdram_cke      (sdram_cke),          //SDRAM 时钟有效
    .sdram_cs_n     (sdram_cs_n),         //SDRAM 片选
    .sdram_ras_n    (sdram_ras_n),        //SDRAM 行有效
    .sdram_cas_n    (sdram_cas_n),        //SDRAM 列有效
    .sdram_we_n     (sdram_we_n),         //SDRAM 写有效
    .sdram_ba       (sdram_ba),           //SDRAM Bank地址
    .sdram_addr     (sdram_addr),         //SDRAM 行/列地址
    .sdram_data     (sdram_data),         //SDRAM 数据
    .sdram_dqm      (sdram_dqm),          //SDRAM 数据掩码
                                          
    .led            (led)                 //状态指示灯
    );  
    
//模型文件
sdr u_sdram(    
    .Clk            (sdram_clk),       
    .Cke            (sdram_cke),       
    .Cs_n           (sdram_cs_n),      
    .Ras_n          (sdram_ras_n),     
    .Cas_n          (sdram_cas_n),     
    .We_n           (sdram_we_n),      
    .Ba             (sdram_ba),        
    .Addr           (sdram_addr),      
    .Dq             (sdram_data),      
    .Dqm            (sdram_dqm)        
    );
    
endmodule 